One common component found in integrated circuits is an electrically conductive line. Such might form part of a device or subcircuit, or interconnect various devices. One common conductive line is a transistor gate of a field effect transistor device. Such are commonly used in memory integrated circuitry, for example dynamic random access memory (DRAM) circuitry. Individual memory cells of DRAM circuitry include a field effect transistor having one source/drain region thereof electrically connected with a storage capacitor, and the other source/drain region electrically connected with a bitline. The conductive transistor gate lines are commonly referred to as wordlines, with individual gate lines constituting a part of several memory cell field effect transistors.
A common wordline construction includes titanium silicide (TiSix) received over conductively doped polysilicon. The titanium silicide might be provided over the polysilicon in a number of manners. For example, elemental titanium might be deposited upon polysilicon and thereafter annealed to react the polysilicon and titanium to form titanium silicide. Alternately by way of examples only, titanium silicide might be chemical vapor deposited upon polysilicon or physical vapor deposited by sputtering from a titanium silicide target. Further and regardless, the titanium silicide which is formed might initially be amorphous or crystalline. Crystallinity is desired for reduced resistance/higher conductance. Amorphous titanium silicide can be converted to crystalline titanium silicide by high temperature anneal.
Crystalline stoichiometric titanium silicide (TiSi2) typically exists in one of two different crystalline phases. A first phase is an orthorhombic base-centered phase having twelve atoms per unit cell, a resistivity of about 60 to 90 microohm-cm, and is known as the C49 phase. A second phase is a more thermodynamically-favored orthorhombic face-centered phase, which has 24 atoms per unit cell and a resistivity of about 12 to 20 microohm-cm, and is known as the C54 phase. Regardless of deposition method, it is common for the less-desired C49 phase to be initially deposited or formed. This C49 phase can then be converted to a desired C54 phase through appropriate annealing conditions.
One problem associated with the fabrication of such lines is known as agglomeration of the titanium silicide relative to the underlying polysilicon. Such typically manifests when the substrate is exposed to temperatures in excess of 900° C. and which typically inherently occurs during the fabrication of the circuitry. Agglomeration is characterized by the titanium silicide migrating/extending into the underlying polysilicon. Such can be to such a degree to extend completely through the polysilicon. For transistor gate lines, the migration can even be to completely through the gate dielectric, thereby causing a fatal short. Further, the degree of agglomeration is not predictable or controllable from device to device. For transistor gates that are not fatally shorted, this undesirably creates different operating characteristics for different devices. Specifically, the degree of agglomeration within the polysilicon affects its work function and, accordingly, the threshold voltage along the gate line at which individual transistors are turned “on” and “off”.
In an effort to reduce titanium silicide agglomeration, previous studies have focused on applying different annealing processes or adding other elements to the titanium silicide. Still, needs remain for improved methods of reducing titanium silicide agglomeration in the fabrication of titanium silicide over polysilicon transistor gate lines, and particularly in the fabrication of DRAM circuitry. Yet while the invention was motivated in addressing these issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.